In general, the term "domino logic" is used to refer to an arrangement of logic circuit stages which may, for example, be cascaded together in an integrated circuit array configuration. A signal may be inputted to a first stage where it is evaluated in order to provide an output signal to a second stage where that output signal is again evaluated to provide an output signal for propagation to and evaluation by yet another stage in the circuit. Thus a "domino" effect is achieved whereby signals are sequentially propagated through an array of "stages" or "domino blocks", and each successive stage performs an evaluation of an input condition until a final output is provided at a final output stage. Domino logic circuits may be arranged so that signals can propagate through the various stages without being separately clocked at each stage.
In traditional differential signal memory arrays utilizing the standard six device cell, four transistors are configured to form a cross-coupled latch/memory cell for storing data and two transistors are used to obtain access to the memory cell. During a "read" access, differential data stored within the memory cell is transferred to an attached bit line pair. Differential voltage is allowed to develop on the bit lines until sufficient offset between bit lines (100-200 mv) has developed to reliably sense the binary state of the memory cell. with the completion of the read, the differential bit line pairs are clamped together and restored high (to a "high" logic level voltage or "VDD") to cancel the offset generated during the read operation.
During a "write" access, data is written into the cell through the differential bit line pair. In general, one side of the bit line pair is driven low (i.e. to a low logic level potential or ground) and the other side of the differential pair is driven high to VDD minus the threshold voltage of the transistor Vt. Following the write, the differential bit line pair must be restored to VDD prior to the next read/write access to the memory cell. For a traditional memory array, the time required for a sufficient bit line offset development to reliably read the memory cell in addition to the time required to restore one-half of the differential bit line pair ground potential to VDD after a write operation defines the minimum cycle time for the array.
Improvements to either the bit line offset development rate, or the bit line restore time following a write, will increase performance of the memory structure as a whole. For a large array, it is more efficient if the array is organized in long column bit lines, i.e. many rows. However, the length of an array bit line is limited by the signal development time for a read. For an array with a long bit line, the signal development time is therefore the most critical path.
Thus there is a need to provide an improved method and apparatus for the implementation of a boost amplifier circuit which is effective to boost the performance of a critical read path in memory cell arrays having extensive bit line layouts.